Multilevel semiconductor device and structure with oxide bonding

ABSTRACT

A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

CROSS-REFERENCE OF RELATED APPLICATION

This application is a continuation-in-part of U.S. patent application Ser. No. 17/717,094 filed on Apr. 10, 2022, now U.S. patent Ser. No. 11/437,368 issued on Sep. 6, 2022; which is a continuation-in-part of U.S. patent application Ser. No. 17/492,627 filed on Oct. 3, 2021, now U.S. Pat. No. 11,327,227 issued on May 10, 2022; which is a continuation-in-part of U.S. patent application Ser. No. 17/330,186 filed on May 5, 2021, now U.S. Pat. No. 11,163,112 issued on Nov. 2, 2021; which is a continuation-in-part of U.S. patent application Ser. No. 17/189,201 filed on Mar. 1, 2021, now U.S. Pat. No. 11,063,071 issued on Jul. 13, 2021; which is a continuation-in-part of U.S. patent application Ser. No. 17/121,726 filed on Dec. 14, 2020, now U.S. Pat. No. 10,978,501 issued on Apr. 13, 2021; which is a continuation-in-part of U.S. patent application Ser. No. 17/027,217 filed on Sep. 21, 2020, now U.S. Pat. No. 10,943,934 issued on Mar. 9, 2021; which is a continuation-in-part of U.S. patent application Ser. No. 16/860,027 filed on Apr. 27, 2020, now U.S. Pat. No. 10,833,108 issued on Nov. 11, 2020; which is a continuation-in-part of U.S. patent application Ser. No. 15/920,499 filed on Mar. 14, 2018, now U.S. Pat. No. 10,679,977 issued on Jun. 9, 2020; which is a continuation-in-part of U.S. patent application Ser. No. 14/936,657 filed on Nov. 9, 2015, now U.S. Pat. No. 9,941,319 issued on Apr. 10, 2018; which is a continuation-in-part of U.S. patent application Ser. No. 13/274,161 filed on Oct. 14, 2011, now U.S. Pat. No. 9,197,804 issued on Nov. 24, 2015; and this application is a continuation-in-part of U.S. patent application Ser. No. 12/904,103 filed on Oct. 13, 2010, now U.S. Pat. No. 8,163,581 issued on Apr. 24, 2012; the entire contents of all of the preceding are incorporated herein by reference.

BACKGROUND OF THE INVENTION (A) Field of the Invention

This invention describes applications of monolithic 3D integration to various disciplines, including but not limited to, for example, light-emitting diodes, displays, image-sensors and solar cells.

(B) Discussion of Background Art

Semiconductor and optoelectronic devices often require thin monocrystalline (or single-crystal) films deposited on a certain wafer. To enable this deposition, many techniques, generally referred to as layer transfer technologies, have been developed. These include:

-   -   Ion-cut, variations of which are referred to as smart-cut,         nano-cleave and smart-cleave: Further information on ion-cut         technology is given in “Frontiers of silicon-on-insulator,” J.         Appl. Phys. 93, 4955-4978 (2003) by G. K. Celler and S.         Cristolovean (“Celler”) and also in “Mechanically induced Si         layer transfer in hydrogen-implanted Si wafers,” Appl. Phys.         Lett., vol. 76, pp. 2370-2372, 2000 by K. Henttinen, I. Suni,         and S. S. Lau (“Hentinnen”).     -   Porous silicon approaches such as ELTRAN: These are described in         “Eltran, Novel SOI Wafer Technology”, JSAP International, Number         4, July 2001 by T. Yonehara and K. Sakaguchi (“Yonehara”).     -   Lift-off with a temporary substrate, also referred to as         epitaxial lift-off. This is described in “Epitaxial lift-off and         its applications”, 1993 Semicond. Sci. Technol. 8 1124 by P.         Demeester, et al (“Demeester”).     -   Bonding a substrate with single crystal layers followed by         Polishing, Time-controlled etch-back or Etch-stop layer         controlled etch-back to thin the bonded substrate: These are         described in U.S. Pat. No. 6,806,171 by A. Ulyashin and A.         Usenko (“Ulyashin”) and “Enabling SOI-Based Assembly Technology         for Three-Dimensional (3D) Integrated Circuits (ICs),” IEDM         Tech. Digest, p. 363 (2005) by A. W. Topol, D. C. La Tulipe, L.         Shi, S. M. Alam, D. J. Frank, S. E. Steen, J. Vichiconti, D.         Posillico, M. Cobb, S. Medd, J. Patel, S. Goma, D.         DiMilia, M. T. Robson, E. Duch, M. Farinelli, C. Wang, R. A.         Conti, D. M. Canaperi, L. Deligianni, A. Kumar, K. T.         Kwietniak, C. D'Emic, J. Ott, A. M. Young, K. W. Guarini, and M.         Ieong (“Topol”).     -   Bonding a wafer with a Gallium Nitride film epitaxially grown on         a sapphire substrate followed by laser lift-off for removing the         transparent sapphire substrate: This method may be suitable for         deposition of Gallium Nitride thin films, and is described in         U.S. Pat. No. 6,071,795 by Nathan W. Cheung, Timothy D. Sands         and William S. Wong (“Cheung”).     -   Rubber stamp layer transfer: This is described in “Solar cells         sliced and diced”, 19 May 2010, Nature News.         With novel applications of these methods and recognition of         their individual strengths and weaknesses, one can significantly         enhance today's light-emitting diode (LED), display,         image-sensor and solar cell technologies.         Background on LEDs

Light emitting diodes (LEDs) are used in many applications, including automotive lighting, incandescent bulb replacements, and as backlights for displays. Red LEDs are typically made on Gallium Arsenide (GaAs) substrates, and include quantum wells constructed of various materials such as AlInGaP and GaInP. Blue and green LEDs are typically made on Sapphire or Silicon Carbide (SiC) or bulk Gallium Nitride (GaN) substrates, and include quantum wells constructed of various materials such as GaN and InGaN.

A white LED for lighting and display applications can be constructed by either using a blue LED coated with phosphor (called phosphor-coated LED or pcLED) or by combining light from red, blue, and green LEDs (called RGB LED). RGB LEDs are typically constructed by placing red, blue, and green LEDs side-by-side. While RGB LEDs are more energy-efficient than pcLEDs, they are less efficient in mixing red, blue and green colors to form white light. They also are much more costly than pcLEDs. To tackle issues with RGB LEDs, several proposals have been made.

One RGB LED proposal from Hong Kong University is described in “Design of vertically stacked polychromatic light emitting diodes”, Optics Express, June 2009 by K. Hui, X. Wang, et al (“Hui”). It involves stacking red, blue, and green LEDs on top of each other after individually packaging each of these LEDs. While this solves light mixing problems, this RGB-LED is still much more costly than a pcLED solution since three LEDs for red, blue, and green color need to be packaged. A pcLED, on the other hand, requires just one LED to be packaged and coated with phosphor.

Another RGB LED proposal from Nichia Corporation is described in “Phosphor Free High-Luminous-Efficiency White Light-Emitting Diodes Composed of InGaN Multi-Quantum Well”, Japanese Journal of Applied Physics, 2002 by M. Yamada, Y. Narukawa, et al. (“Yamada”). It involves constructing and stacking red, blue and green LEDs of GaN-based materials on a sapphire or SiC substrate. However, red LEDs are not efficient when constructed with GaN-based material systems, and that hampers usefulness of this implementation. It is not possible to deposit defect-free AlInGaP/InGaP for red LEDs on the same substrate as GaN based blue and green LEDs, due to a mismatch in thermal expansion co-efficient between the various material systems.

Yet another RGB-LED proposal is described in “Cascade Single chip phosphor-free while light emitting diodes”, Applied Physics Letters, 2008 by X. Guo, G. Shen, et al. (“Guo”). It involves bonding GaAs based red LEDs with GaN based blue-green LEDs to produce white light. Unfortunately, this bonding process requires 600° C. temperatures, causing issues with mismatch of thermal expansion co-efficients and cracking. Another publication on this topic is “A trichromatic phosphor-free white light-emitting diode by using adhesive bonding scheme”, Proc. SPIE, Vol. 7635, 2009 by D. Chuai, X. Guo, et al. (“Chuai”). It involves bonding red LEDs with green-blue LED stacks. Bonding is done at the die level after dicing, which is more costly than a wafer-based approach.

U.S. patent application Ser. No. 12/130,824 describes various stacked RGB LED devices. It also briefly mentions a method for construction of a stacked LED where all layers of the stacked LED are transferred using lift-off with a temporary carrier and Indium Tin Oxide (ITO) to semiconductor bonding. This method has several issues for constructing a RGB LED stack. First, it is difficult to manufacture a lift-off with a temporary carrier of red LEDs for producing a RGB LED stack, especially for substrates larger than 2 inch. This is because red LEDs are typically constructed on non-transparent GaAs substrates, and lift-off with a temporary carrier is done by using an epitaxial lift-off process. Here, the thin film to be transferred typically sits atop a “release-layer” (eg. AlAs), this release layer is removed by etch procedures after the thin film is attached to a temporary substrate. Scaling this process to 4 inch wafers and bigger is difficult. Second, it is very difficult to perform the bonding of ITO to semiconductor materials of a LED layer at reasonable temperatures, as described in the patent application Ser. No. 12/130,824.

It is therefore clear that a better method for constructing RGB LEDs will be helpful. Since RGB LEDs are significantly more efficient than pcLEDs, they can be used as replacements of today's phosphor-based LEDs for many applications, provided a cheap and effective method of constructing RGB LEDs can be invented.

Background on Image-Sensors:

Image sensors are used in applications such as cameras. Red, blue, and green components of the incident light are sensed and stored in digital format. CMOS image sensors typically contain a photodetector and sensing circuitry. Almost all image sensors today have both the photodetector and sensing circuitry on the same chip. Since the area consumed by the sensing circuits is high, the photodetector cannot see the entire incident light, and image capture is not as efficient.

To tackle this problem, several researchers have proposed building the photodetectors and the sensing circuitry on separate chips and stacking them on top of each other. A publication that describes this method is “Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology”, Intl. Solid State Circuits Conference 2005 by Suntharalingam, V., Berger, R., et al. (“Suntharalingam”). These proposals use through-silicon via (TSV) technology where alignment is done in conjunction with bonding. However, pixel size is reaching the 1 μm range, and successfully processing TSVs in the 1 μm range or below is very difficult. This is due to alignment issues while bonding. For example, the International Technology Roadmap for Semiconductors (ITRS) suggests that the 2-4 um TSV pitch will be the industry standard until 2012. A 2-4 μm pitch TSV will be too big for a sub-1 μm pixel. Therefore, novel techniques of stacking photodetectors and sensing circuitry are required.

A possible solution to this problem is given in “Setting up 3D Sequential Integration for Back-Illuminated CMOS Image Sensors with Highly Miniaturized Pixels with Low Temperature Fully-depleted SOI Transistors,” IEDM, p. 1-4 (2008) by P. Coudrain et al. (“Coudrain”). In the publication, transistors are monolithically integrated on top of photodetectors. Unfortunately, transistor process temperatures reach 600° C. or more. This is not ideal for transistors (that require a higher thermal budget) and photodetectors (that may prefer a lower thermal budget).

Background on Displays:

Liquid Crystal Displays (LCDs) can be classified into two types based on manufacturing technology utilized: (1) Large-size displays that are made of amorphous/polycrystalline silicon thin-film-transistors (TFTs), and (2) Microdisplays that utilize single-crystal silicon transistors. Microdisplays are typically used where very high resolution is needed, such as camera/camcorder view-finders, projectors and wearable computers.

Microdisplays are made in semiconductor fabs with 200 mm or 300 mm wafers. They are typically constructed with LCOS (Liquid-Crystal-on-Silicon) Technology and are reflective in nature. An exception to this trend of reflective microdisplays is technology from Kopin Corporation (U.S. Pat. No. 5,317,236, filed December 1991). This company utilizes transmittive displays with a lift-off layer transfer scheme. Transmittive displays may be generally preferred for various applications.

While lift-off layer transfer schemes are viable for transmittive displays, they are frequently not used for semiconductor manufacturing due to yield issues. Therefore, other layer transfer schemes will be helpful. However, it is not easy to utilize other layer transfer schemes for making transistors in microdisplays. For example, application of “smart-cut” layer transfer to attach monocrystalline silicon transistors to glass is described in “Integration of Single Crystal Si TFTs and Circuits on a Large Glass Substrate”, IEDM 2009 by Y. Takafuji, Y. Fukushima, K. Tomiyasu, et al. (“Takafuji”). Unfortunately, hydrogen is implanted through the gate oxide of transferred transistors in the process, and this degrades performance. Process temperatures are as high as 600° C. in this paper, and this requires costly glass substrates. Several challenges therefore need to be overcome for efficient layer transfer, and require innovation.

Background on Solar Cells:

Solar cells can be constructed of several materials such as, for example, silicon and compound semiconductors. The highest efficiency solar cells are typically multi junction solar cells that are constructed of compound semiconductor materials. These multi junction solar cells are typically constructed on a germanium substrate, and semiconductors with various band-gaps are epitaxially grown atop this substrate to capture different portions of the solar spectrum.

There are a few issues with standard multi junction solar cells. Since multiple junctions are grown epitaxially above a single substrate (such as Germanium) at high temperature, materials used for different junctions are restricted to those that have lattice constants and thermal expansion co-efficients close to those of the substrate. Therefore, the choice of materials used to build junctions for multi junction solar cells is limited. As a result, most multi junction solar cells commercially available today cannot capture the full solar spectrum. Efficiency of the solar cell can be improved if a large band of the solar spectrum is captured. Furthermore, multi junction solar cells today suffer from high cost of the substrate above which multiple junctions are epitaxially grown. Methods to build multi junction solar cells that tackle both these issues will be helpful.

A method of making multi junction solar cells by mechanically bonding two solar cells, one with a Germanium junction and another with a compound semiconductor junction is described in “Towards highly efficient 4-terminal mechanical photovoltaic stacks”, III-Vs Review, Volume 19, Issue 7, September-October 2006 by Giovanni Flamand, Jef Poortmans (“Flamand”). In this work, the authors make the compound semiconductor junctions on a Germanium substrate epitaxially. They then etch away the entire Germanium substrate after bonding to the other substrate with the Germanium junction. The process uses two Germanium substrates, and is therefore expensive.

Techniques to create multi junction solar cells with layer transfer have been described in “Wafer bonding and layer transfer processes for 4-junction high efficiency solar cells,” Photovoltaic Specialists Conference, 2002. Conference Record of the Twenty-Ninth IEEE, vol., no., pp. 1039-1042, 19-24 May 2002 by Zahler, J. M.; Fontcuberta i Morral, A.; Chang-Geun Ahn; Atwater, H. A.; Wanlass, M. W.; Chu, C. and Iles, P. A. An anneal is used for ion-cut purposes, and this anneal is typically done at temperatures higher than 350-400° C. (if high bond strength is desired). When that happens, cracking and defects can be produced due to mismatch of co-efficients of thermal expansion between various layers in the stack. Furthermore, semiconductor layers are bonded together, and the quality of this bond not as good as oxide-to-oxide bonding, especially for lower process temperatures.

Background on CCD Sensors:

Image sensors based on Charge-Coupled Device (CCD) technology has been around for several decades. The CCD technology relies on a collect and shift scheme, wherein charges are collected in individual cells according to the luminosity of the light falling on each of them, then the charges are sequentially shifted towards one edge of the sensor where readout circuits read the sequence of charges one at a time.

The advantage of CCD technology is it has better light sensitivity since almost the entire CCD cell area is dedicated to light collecting, and the control and readout circuits are all on one edge not blocking the light. On the other hand, in a CMOS sensor, the photodiodes in each cell have to share space with the control and readout circuits adjacent to them, and so their size and light sensitivity are therefore limited.

The main issue with CCD technology is this sequential shifting of image information from cell to cell is slow and limits the speed and cell density of CCD image sensors. A potential solution is to put the readout circuits directly under each CCD cell, so that the information is read in parallel rather than in time sequence, thus removing the shifting delay entirely.

Background on High Dynamic Range (HDR) Sensors:

Ever since the advent of commercial digital photography in the 1990s, achieving High Dynamic Range (HDR) imaging has been a goal for most camera manufacturers in their image sensors. The idea is to use various techniques to compensate for the lower dynamic range of image sensors relative to the human eye. The concept of HDR however, is not new. Combining multiple exposures of a single image to achieve a wide range of luminosity was actually pioneered in the 1850s by Gustave Le Gray to render seascapes showing both the bright sky and the dark sea. This was necessary to produce realistic photographic images as the film used at that time had extremely low dynamic range compared to the human eye.

In digital cameras, the typical approach is to capture images using exposure bracketing, and then combining them into a single HDR image. The issue with this is that multiple exposures are performed over some period of time, and if there is movement of the camera or target during the time of the exposures, the final HDR image will reflect this by loss of sharpness. Moreover, multiple images may lead to large data in storage devices. Other methods use software algorithms to extract HDR information from a single exposure, but as they can only process information that is recordable by the sensor, there is a permanent loss of some details.

Over the past 40 years, there has been a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling”; i.e., component sizes within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today is that wires dominate the performance, functionality and power consumption of ICs.

3D stacking of semiconductor devices or chips is one avenue to tackle the wire issues. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), the transistors in ICs can be placed closer to each other. This reduces wire lengths and keeps wiring delay low.

There are many techniques to construct 3D stacked integrated circuits or chips including:

Through-silicon via (TSV) technology: Multiple layers of transistors (with or without wiring levels) can be constructed separately. Following this, they can be bonded to each other and connected to each other with through-silicon vias (TSVs).

Monolithic 3D technology: With this approach, multiple layers of transistors and wires can be monolithically constructed. Some monolithic 3D and 3DIC approaches are described in U.S. Pat. Nos. 8,273,610, 8,298,875, 8,362,482, 8,378,715, 8,379,458, 8,450,804, 8,557,632, 8,574,929, 8,581,349, 8,642,416, 8,669,778, 8,674,470, 8,687,399, 8,742,476, 8,803,206, 8,836,073, 8,902,663, 8,994,404, 9,023,688, 9,029,173, 9,030,858, 9,117,749, 9,142,553, 9,219,005, 9,385,058, 9,406,670, 9,460,978, 9,509,313, 9,640,531, 9,691,760, 9,711,407, 9,721,927, 9,799,761, 9,871,034, 9,953,870, 9,953,994, 10,014,292, 10,014,318, 10,515,981, 10,892,016; and pending U.S. Patent Application Publications and applications, Ser. Nos. 14/642,724, 15/150,395, 15/173,686, 16/337,665, 16/558,304, 16/649,660, 16/836,659, 17/151,867, 62/651,722; 62/681,249, 62/713,345, 62/770,751, 62/952,222, 62/824,288, 63/075,067, 63/091,307, 63/115,000, 63/220,443, 2021/0242189, 2020/0013791, 16/558,304; and PCT Applications (and Publications): PCT/US2010/052093, PCT/US2011/042071 (WO2012/015550), PCT/US2016/52726 (WO2017053329), PCT/US2017/052359 (WO2018/071143), PCT/US2018/016759 (WO2018144957), PCT/US2018/52332 (WO 2019/060798), and PCT/US2021/44110. The entire contents of all of the foregoing patents, publications, and applications are incorporated herein by reference.

Electro-Optics: There is also work done for integrated monolithic 3D including layers of different crystals, such as U.S. Pat. Nos. 8,283,215, 8,163,581, 8,753,913, 8,823,122, 9,197,804, 9,419,031, 9,941,319, 10,679,977, 10,943,934, 10,998,374, 11,063,071, and 11,133,344. The entire contents of all of the foregoing patents, publications, and applications are incorporated herein by reference.

In addition, the entire contents of U.S. Pat. Nos. 8,273,610, 9,000,557, 8,753,913, 8,823,122, 9,419,031, 9,197,804, 9,941,319, 10,679,977, 10,833,108, 10,943,934, 10,978,501, 10,998,374, 11,063,071, 11,133,344, 11,163,112, 11,164,898, 11,315,965, 11,327,227 and U.S. Patent Application Publication 2020/0194416, and U.S. patent application Ser. No. 17/402,527; are incorporated herein by reference.

SUMMARY

Techniques to utilize layer transfer schemes such as ion-cut to form novel light emitting diodes (LEDs), CMOS image sensors, displays, microdisplays and solar cells are discussed.

In one aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an optical waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including an optical waveguide; a second level including integrated circuits, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a plurality of optical modulators, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an electromagnetic waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including an electromagnetic waveguide; a second level including integrated circuits, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a plurality of electromagnetic modulators, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves in a confined manner, where the second level is disposed above the first level, where the first level includes crystalline silicon, where the second level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including a structure designed to conduct electromagnetic waves in a confined manner; a second level including integrated circuits, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a plurality of electromagnetic modulators, where the second level is disposed above the first level, where the first level includes crystalline silicon, where the second level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the first level.

In another aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon, where the second level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including a structure designed to conduct electromagnetic waves; a second level including integrated circuits, where the second level is disposed above the first level; a plurality of electromagnetic modulators; and an oxide layer disposed between the first level and the second level, where the first level includes crystalline silicon, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits and electromagnetic modulators; a second level including a plurality of transistors, where the second level is disposed above the first level, where the first level includes crystalline silicon, where the second level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the first level.

In another aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including a structure designed to conduct electromagnetic waves; a second level including integrated circuits, where the second level is disposed above the first level; a plurality of electromagnetic modulators; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits and electromagnetic modulators; a second level including a plurality of interconnects lines, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level; where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including a structure designed to conduct electromagnetic waves; a second level including integrated circuits, where the second level is disposed above the first level, and at least one transmitter and at least one receiver; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits and communication control circuits; a second level including a plurality of interconnect lines, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including a structure designed to conduct electromagnetic waves; a second level including integrated circuits, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the device including: a first level including integrated circuits and communication control circuits; a second level including a plurality of interconnect lines, where the second level is disposed above the first level, where the first level includes a crystalline material; an oxide layer disposed between the first level and the second level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds; and at least one electromagnetic wave receiver.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments of the invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:

FIGS. 1A-1G are exemplary drawn illustrations of a display constructed using sub-400° C. processed single crystal silicon recessed channel transistors on a glass substrate;

FIGS. 2A-2I are exemplary drawn illustrations of a display constructed using sub-400° C. processed single crystal silicon replacement gate transistors on a glass substrate;

FIGS. 3A-3F are exemplary drawn illustrations of a display constructed using sub-400° C. processed single crystal junction-less transistors on a glass substrate;

FIGS. 4A-4D are exemplary drawn illustrations of a display constructed using sub-400° C. processed amorphous silicon or polysilicon junctionless transistors on a glass substrate;

FIGS. 5A-5C are exemplary drawn illustrations of a microdisplay constructed using stacked RGB LEDs and control circuits are connected to each pixel with solder bumps;

FIGS. 6A-6D are exemplary drawn illustrations of a microdisplay constructed using stacked RGB LEDs and control circuits are monolithically stacked above the LED. FIGS. 31A-H illustrate an embodiment of this invention, where a LED-driven chip-to-chip optical interconnect is constructed by monolithically stacking using layer transfer techniques;

FIGS. 7A-7H illustrate an embodiment of this invention, where a LED-driven chip-to-chip optical interconnect is constructed by monolithically stacking using layer transfer techniques;

FIGS. 8A-8D illustrate an embodiment of this invention, where a laser-driven chip-to-chip optical interconnect is constructed by monolithically stacking using layer transfer techniques;

FIGS. 9A-9C illustrate an embodiment of this invention, where a LED-driven on-chip optical interconnect is constructed by monolithically stacking using layer transfer techniques;

FIG. 10 illustrates a typical hollow-metal waveguide (HMWG) structure which enables on-chip communication via waveguides stacked on top of the active layer of the chip (prior art); and

FIGS. 11A-11C illustrate an embodiment of this invention, where a laser-driven on-chip optical interconnect is constructed by monolithically stacking using layer transfer techniques.

DETAILED DESCRIPTION

Embodiments of the present invention are now described with reference to FIGS. 1-11 , it being appreciated that the figures illustrate the subject matter not to scale or to measure.

A smart layer transfer may be defined as one or more of the following processes:

-   -   Ion-cut, variations of which are referred to as smart-cut,         nano-cleave and smart-cleave: Further information on ion-cut         technology is given in “Frontiers of silicon-on-insulator,” J.         Appl. Phys. 93, 4955-4978 (2003) by G. K. Celler and S.         Cristolovean (“Celler”) and also in “Mechanically induced Si         layer transfer in hydrogen-implanted Si wafers,” Appl. Phys.         Lett., vol. 76, pp. 2370-2372, 2000 by K. Henttinen, I. Suni,         and S. S. Lau (“Hentinnen”).     -   Porous silicon approaches such as ELTRAN: These are described in         “Eltran, Novel SOI Wafer Technology,” JSAP International, Number         4, July 2001 by T. Yonehara and K. Sakaguchi (“Yonehara”).     -   Bonding a substrate with single crystal layers followed by         Polishing, Time-controlled etch-back or Etch-stop layer         controlled etch-back to thin the bonded substrate: These are         described in U.S. Pat. No. 6,806,171 by A. Ulyashin and A.         Usenko (“Ulyashin”) and “Enabling SOI-Based Assembly Technology         for Three-Dimensional (3D) Integrated Circuits (ICs),” IEDM         Tech. Digest, p. 363 (2005) by A. W. Topol, D. C. La Tulipe, L.         Shi, S. M. Alam, D. J. Frank, S. E. Steen, J. Vichiconti, D.         Posillico, M. Cobb, S. Medd, J. Patel, S. Goma, D.         DiMilia, M. T. Robson, E. Duch, M. Farinelli, C. Wang, R. A.         Conti, D. M. Canaperi, L. Deligianni, A. Kumar, K. T.         Kwietniak, C. D'Emic, J. Ott, A. M. Young, K. W. Guarini, and M.         Ieong (“Topol”).     -   Bonding a wafer with a Gallium Nitride film epitaxially grown on         a sapphire substrate followed by laser lift-off for removing the         transparent sapphire substrate: This method may be suitable for         deposition of Gallium Nitride thin films, and is described in         U.S. Pat. No. 6,071,795 by Nathan W. Cheung, Timothy D. Sands         and William S. Wong (“Cheung”).     -   Rubber stamp layer transfer: This is described in “Solar cells         sliced and diced,” 19 May 2010, Nature News.

This process of constructing RGB LEDs could include several steps that occur in a sequence from Step (A) to Step (S). Many of them share common characteristics, features, modes of operation, etc. When the same reference numbers are used in different drawing figures, they are used to indicate analogous, similar or identical structures to enhance the understanding of the present invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.

NuDisplay Technology:

In displays and microdisplays (small size displays where optical magnification is needed), transistors need to be formed on glass or plastic substrates. These substrates typically cannot withstand high process temperatures (e.g., >400° C.). Layer transfer can be advantageously used for constructing displays and microdisplays as well, since it may enable transistors to be processed on these substrates at <400° C. Various embodiments of transistors constructed on glass substrates are described in this patent application. These transistors constructed on glass substrates could form part of liquid crystal displays (LCDs) or other types of displays. It will be clear to those skilled in the art based on the present disclosure that these techniques can also be applied to plastic substrates.

FIGS. 1A-1G describe a process for forming recessed channel single crystal (or monocrystalline) transistors on glass substrates at a temperature approximately less than 400° C. for display and microdisplay applications. This process could include several steps that occur in a sequence from Step (A) to Step (G). Many of these steps share common characteristics, features, modes of operation, etc. When identical reference numbers are used in different drawing figures, they are used to indicate analogous, similar or identical structures to enhance the understanding of the present invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.

Step (A) is illustrated in FIG. 1A. A silicon wafer 2202 is taken and a n+ region 2204 is formed by ion implantation. Following this formation, a layer of p− Silicon 2206 is epitaxially grown. An oxide layer 2210 is then deposited. Following this deposition, an anneal is performed to activate dopants in various layers. It will be clear to one skilled in the art based on the present disclosure that various other procedures can be used to get the structure shown in FIG. 22A. Step (B) is illustrated in FIG. 1B. Hydrogen is implanted into the structure shown in FIG. 22A at a certain depth indicated by 2212. Alternatively, Helium can be used for this purpose. Various elements in FIG. 1B, such as 2202, 2204, 2006, and 2210 have been described previously. Step (C) is illustrated in FIG. 1C. A glass substrate 2214 is taken and a silicon oxide layer 2216 is deposited atop it at compatible temperatures. Step (D) is illustrated in FIG. 1D. Various elements in FIG. 1D, such as 2202, 2204, 2206, 2210, 2214, and 2216 have been described previously. The structure shown in FIG. 1B is flipped and bonded to the structure shown in FIG. 1C using oxide-to-oxide bonding of layers 2210 and 2216. Step (E) is illustrated in FIG. 1E. The structure shown in FIG. 1D is cleaved at the hydrogen plane 2212 of FIG. 1D. A CMP is then done to planarize the surface and yield the n+Si layer 2218. Various other elements in FIG. 1E, such as 2214, 2216, 2210 and 2206 have been described previously. Step (F) is illustrated in FIG. 1F. Various elements in FIG. 1F such as 2214, 2216, 2210, and 2206 have been described previously. An oxide layer 2220 is formed using a shallow trench isolation (STI) process. This helps isolate transistors. Step (G) is illustrated in FIG. 1G. Various elements in FIG. 1G such as 2210, 2216, 2220 and 2214 have been described previously. Using etch techniques, part of the n+ Silicon layer from FIG. 1F and optionally p− Silicon layer from FIG. 1F are etched. After this a thin gate dielectric is deposited, after which a gate dielectrode is deposited. The gate dielectric and gate electrode are then polished away to form the gate dielectric layer 2224 and gate electrode layer 2222. The n+ Silicon layers 2228 and 2226 form the source and drain regions of the transistors while the p− Silicon region after this step is indicated by 2230. Contacts and other parts of the display/microdisplay are then fabricated. It can be observed that during the whole process, the glass substrate substantially always experiences temperatures less than 400° C., or even lower. This is because the crystalline silicon can be transferred atop the glass substrate at a temperature less than 400° C., and dopants are pre-activated before layer transfer to glass.

FIG. 2A-2I describes a process of forming both nMOS and pMOS transistors with single-crystal silicon on a glass substrate at temperatures less than 400° C., and even lower. Ion-cut technology (which is a smart layer transfer technology) is used. While the process flow described is shown for both nMOS and pMOS on a glass substrate, it could also be used for just constructing nMOS devices or for just constructing pMOS devices. This process could include several steps that occur in a sequence from Step (A) to Step (H). Many of these steps share common characteristics, features, modes of operation, etc. When identical reference numbers are used in different drawing figures, they are used to indicate analogous, similar or identical structures to enhance the understanding of the present invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.

Step (A) is illustrated in FIG. 2A. A p− Silicon wafer 2302 is taken and a n well 2304 is formed on the p− Silicon wafer 2302. Various additional implants to optimize dopant profiles can also be done. Following this formation, an isolation process is conducted to form isolation regions 2306. A dummy gate dielectric 2310 made of silicon dioxide and a dummy gate electrode 2308 made of polysilicon are constructed. Step (B) is illustrated in FIG. 2B. Various elements of FIG. 2B, such as 2302, 2304, 2306, 2308 and 2310 have been described previously. Implants are done to form source-drain regions 2312 and 2314 for both nMOS and pMOS transistors. A rapid thermal anneal (RTA) is then done to activate dopants. Alternatively, a spike anneal or a laser anneal could be done. Step (C) is illustrated in FIG. 2C. Various elements of FIG. 2C such as 2302, 2304, 2306, 2308, 2310, 2312 and 2314 have been described previously. An oxide layer 2316 is deposited and planarized with CMP. Step (D) is illustrated in FIG. 2D. Various elements of FIG. 2D such as 2302, 2304, 2306, 2308, 2310, 2312, 2314, and 2316 have been described previously. Hydrogen is implanted into the wafer at a certain depth indicated by 2318. Alternatively, helium can be implanted. Step (E) is illustrated in FIG. 2E. Various elements of FIG. 2E such as 2302, 2304, 2306, 2308, 2310, 2312, 2314, 2316, and 2318 have been described previously. Using a temporary bonding adhesive, the oxide layer is bonded to a temporary carrier wafer 2320. An example of a temporary bonding adhesive is a polyimide that can be removed by shining a laser. An example of a temporary carrier wafer is glass. Step (F) is illustrated in FIG. 2F. The structure shown in FIG. 2E is cleaved at the hydrogen plane using a mechanical force. Alternatively, an anneal could be used. Following this cleave, a CMP is done to planarize the surface. An oxide layer is then deposited. FIG. 2F shows the structure after all these steps are done, with the deposited oxide layer indicated as 2328. After the cleave, the p− Silicon region is indicated as 2322, the n− Silicon region is indicated as 2324, and the oxide isolation regions are indicated as 2326. Various other elements in FIG. 23F such as 2308, 2320, 2312, 2314, 2310, and 2316 have been described previously. Step (G) is illustrated in FIG. 2G. The structure shown in FIG. 2F is bonded to a glass substrate 2332 with an oxide layer 2330 using oxide-to-oxide bonding. Various elements in FIG. 2G such as 2308, 2326, 2322, 2324, 2312, 2314, and 2310 have been described previously. Oxide regions 2328 and 2330 are bonded together. The temporary carrier wafer from FIG. 2F is removed by shining a laser through it. A CMP process is then conducted to reach the surface of the gate electrode 2308. Thus, the structure may be illustrated by FIG. 2H. The oxide layer remaining is denoted as 2334. Step (H) is illustrated in FIG. 2I. Various elements in FIG. 2I such as 2312, 2314, 2328, 2330, 2332, 2334, 2326, 2324, and 2322 have been described previously. The dummy gate dielectric and dummy gate electrode are etched away in this step and a replacement gate dielectric 2336 and a replacement gate electrode 2338 are deposited and planarized with CMP. Examples of replacement gate dielectrics could be hafnium oxide or aluminum oxide while examples of replacement gate electrodes could be TiN or TaN or some other material. Contact formation, metallization and other steps for building a display/microdisplay are then conducted. It can be observed that after attachment to the glass substrate, no process step requires a processing temperature above 400° C.

FIGS. 3A-3F describe an embodiment of this invention, where single-crystal Silicon junction-less transistors are constructed above glass substrates at a temperature approximately less than 400° C. An ion-cut process (which is a smart layer transfer process) is utilized for this purpose. This process could include several steps that occur in a sequence from Step (A) to Step (F). Many of these steps share common characteristics, features, modes of operation, etc. When identical reference numbers are used in different drawing figures, they are used to indicate analogous, similar or identical structures to enhance the understanding of the present invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.

Step (A) is illustrated in FIG. 3A. A glass substrate 2402 is taken and a layer of silicon oxide 2404 is deposited on the glass substrate 2402.

Step (B) is illustrated in FIG. 3B. A p− Silicon wafer 2406 is implanted with a n+ Silicon layer 2408 above which an oxide layer 2410 is deposited. A RTA or spike anneal or laser anneal is conducted to activate dopants. Following this, hydrogen is implanted into the wafer at a certain depth indicated by 2412. Alternatively, helium can be implanted. Step (C) is illustrated in FIG. 3C. The structure shown in FIG. 3B is flipped and bonded onto the structure shown in FIG. 3A using oxide-to-oxide bonding. This bonded structure is cleaved at its hydrogen plane, after which a CMP is done. FIG. 3C shows the structure after all these processes are completed. 2414 indicates the n+Si layer, while 2402, 2404, and 2410 have been described previously. Step (D) is illustrated in FIG. 3D. A lithography and etch process is conducted to pattern the n+ Silicon layer 2414 in FIG. 3C to form n+ Silicon regions 2418 in FIG. 3D. The glass substrate is indicated as 2402 and the bonded oxide layers 2404 and 2410 are shown as well. Step (E) is illustrated in FIG. 3E. A gate dielectric 2420 and gate electrode 2422 are deposited, following which a CMP is done. 2402 is as described previously. The n+Si regions 2418 are not visible in this figure, since they are covered by the gate electrode 2422. Oxide regions 2404 and 2410 have been described previously. Step (F) is illustrated in FIG. 3F. The gate dielectric 2420 and gate electrode 2422 from FIG. 3E are patterned and etched to form the structure shown in FIG. 3F. The gate dielectric after the etch process is indicated as 2424 while the gate electrode after the etch process is indicated as 2426. n+Si regions are indicated as 2418 while the glass substrate is indicated as 2402. Oxide regions 2404 and 2410 have been described previously. It can be observed that a three-side gated junction-less transistor is formed at the end of the process described with respect of FIGS. 3A-3F. Contacts, metallization and other steps for constructing a display/microdisplay are performed after the steps indicated by FIGS. 3A-3F. It can be seen that the glass substrate is not exposed to temperatures greater than approximately 400° C. during any step of the above process for forming the junction-less transistor.

FIGS. 4A-D describe an embodiment of this invention, where amorphous Si or polysilicon junction-less transistors are constructed above glass substrates at a temperature less than 400° C. This process could include several steps that occur in a sequence from Step (A) to Step (D). Many of these steps share common characteristics, features, modes of operation, etc. When identical reference numbers are used in different drawing figures, they are used to indicate analogous, similar or identical structures to enhance the understanding of the present invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.

Step (A) is illustrated in FIG. 4A. A glass substrate 2502 is taken and a layer of silicon oxide 2504 is deposited on the glass substrate 2502. Following this deposition, a layer of n+Si 2506 is deposited using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). This layer of n+Si could optionally be hydrogenated. Step (B) is illustrated in FIG. 4B. A lithography and etch process is conducted to pattern the n+ Silicon layer 2506 in FIG. 4A to form n+ Silicon regions 2518 in FIG. 4B. 2502 and 2504 have been described previously. Step (C) is illustrated in FIG. 4C. A gate dielectric 2520 and gate electrode 2522 are deposited, following which a CMP is optionally done. 2502 is as described previously. The n+Si regions 2518 are not visible in this figure, since they are covered by the gate electrode 2522. Step (D) is illustrated in FIG. 4D. The gate dielectric 2520 and gate electrode 2522 from FIG. 4C are patterned and etched to form the structure shown in FIG. 4D. The gate dielectric after the etch process is indicated as 2524 while the gate electrode after the etch process is indicated as 2526. n+Si regions are indicated as 2518 while the glass substrate is indicated as 2502. It can be observed that a three-side gated junction-less transistor is formed at the end of the process described with respect of FIGS. 4A-4D. Contacts, metallization and other steps for constructing a display/microdisplay are performed after the steps indicated by FIGS. 4A-4D. It can be seen that the glass substrate is not exposed to temperatures greater than 400° C. during any step of the above process for forming the junction-less transistor.

FIGS. 5A-5C illustrate an embodiment of this invention, where a microdisplay is constructed using stacked RGB LEDs and control circuits are connected to each pixel with solder bumps. This process could include several steps that occur in a sequence from Step (A) to Step (C). Many of these steps share common characteristics, features, modes of operation, etc. When identical reference numbers are used in different drawing figures, they are used to indicate analogous, similar or identical structures to enhance the understanding of the present invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.

Step (A) is illustrated in FIG. 5A. Using procedures similar to FIG. 4A-4S of parent U.S. patent application Ser. No. 13/274,161 issued as U.S. Pat. No. 9,197,804, incorporated herein by reference, the structure shown in FIG. 5A is constructed. Various elements of FIG. 5A are as follows:

-   2646—a glass substrate, -   2644—an oxide layer, could be a conductive oxide such as ITO, -   2634—an oxide layer, could be a conductive oxide such as ITO -   2633—a an optional reflector, could be a Distributed Bragg Reflector     or some other type of reflector, -   2632—a P-type confinement layer that is used for a Blue LED (One     example of a material for this region is GaN), -   2630—a buffer layer that is typically used for a Blue LED (One     example of a material for this region is AlGaN), -   2628—a multiple quantum well used for a Blue LED (One example of     materials for this region are InGaN/GaN), -   2627—a N-type confinement layer that is used for a Blue LED (One     example of a material for this region is GaN). -   2648—an oxide layer, may be preferably a conductive metal oxide such     as ITO, -   2622—an oxide layer, may be preferably a conductive metal oxide such     as ITO, -   2621—an optional reflector (for example, a Distributed Bragg     Reflector), -   2620—a P-type confinement layer that is used for a Green LED (One     example of a material for this region is GaN), -   2618—a buffer layer that is typically used for a Green LED (One     example of a material for this region is AlGaN), -   2616—a multiple quantum well used for a Green LED (One example of     materials for this region are InGaN/GaN), -   2615—a N-type confinement layer that is used for a Green LED (One     example of a material for this region is GaN), -   2652—an oxide layer, may be preferably a conductive metal oxide such     as ITO, -   2610—an oxide layer, may be preferably a conductive metal oxide such     as ITO, -   2609—an optional reflector (for example, a Distributed Bragg     Reflector), -   2608—a P-type confinement layer used for a Red LED (One example of a     material for this region is AlInGaP), -   2606—a multiple quantum well used for a Red LED (One example of     materials for this region are AlInGaP/GaInP), -   2604—a P-type confinement layer used for a Red LED (One example of a     material for this region is AlInGaP), -   2656—an oxide layer, may be preferably a transparent conductive     metal oxide such as ITO, and -   2658—a reflector (for example, aluminum or silver).     Step (B) is illustrated in FIG. 5B. Via holes 2662 are etched to the     substrate layer 2646 to isolate different pixels in the     microdisplay/display. Also, via holes 2660 are etched to make     contacts to various layers of the stack. These via holes may be     preferably not filled. An alternative is to fill the via holes with     a compatible oxide and planarize the surface with CMP. Various     elements in FIG. 5B such as 2646, 2644, 2634, 2633, 2632, 2630,     2628, 2627, 2648, 2622, 2621, 2620, 2618, 2616, 2615, 2652, 2610,     2609, 2608, 2606, 2604, 2656 and 2658 have been described     previously.     Step (C) is illustrated in FIG. 5C. Using procedures similar to     those described in respect to FIGS. 4A-4S of parent U.S. patent     application Ser. No. 13/274,161 issued as U.S. Pat. No. 9,197,804,     incorporated herein by reference, the via holes 2660 have contacts     2664 (for example, with Aluminum) made to them. Also, using     procedures similar to those described in FIGS. 4A-4S, nickel layers     2666, solder layers 2668, and a silicon sub-mount 2670 with circuits     integrated on them are constructed. The silicon sub-mount 2670 has     transistors to control each pixel in the microdisplay/display.     Various elements in FIG. 5C such as 2646, 2644, 2634, 2633, 2632,     2630, 2628, 2627, 2648, 2622, 2621, 2620, 2618, 2616, 2615, 2652,     2610, 2609, 2608, 2606, 2604, 2656, 2660, 2662, and 2658 have been     described previously.     It can be seen that the structure shown in FIG. 5C can have each     pixel emit a certain color of light by tuning the voltage given to     the red, green and blue layers within each pixel. This microdisplay     may be constructed using the ion-cut technology, a smart layer     transfer technique.

FIGS. 6A-6D illustrate an embodiment of this invention, where a microdisplay is constructed using stacked RGB LEDs and control circuits are integrated with the RGB LED stack. This process could include several steps that occur in a sequence from Step (A) to Step (D). Many of these steps share common characteristics, features, modes of operation, etc. When identical reference numbers are used in different drawing figures, they are used to indicate analogous, similar or identical structures to enhance the understanding of the present invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.

Step (A) is illustrated in FIG. 6A. Using procedures similar to those illustrated in FIGS. 4A-4S of parent U.S. patent application Ser. No. 13/274,161 issued as U.S. Pat. No. 9,197,804, incorporated herein by reference, the structure shown in FIG. 6A is constructed. Various elements of FIG. 6A are as follows:

-   2746—a glass substrate, -   2744—an oxide layer, could be a conductive oxide such as ITO, -   2734—an oxide layer, could be a conductive oxide such as ITO, -   2733—a an optional reflector (e.g., a Distributed Bragg Reflector or     some other type of reflector), -   2732—a P-type confinement layer that is used for a Blue LED (One     example of a material for this region is GaN), -   2730—a buffer layer that is typically used for a Blue LED (One     example of a material for this region is AlGaN), -   2728—a multiple quantum well used for a Blue LED (One example of     materials for this region are InGaN/GaN), -   2727—a N-type confinement layer that is used for a Blue LED (One     example of a material for this region is GaN), -   2748—an oxide layer, may be preferably a conductive metal oxide such     as ITO, -   2722—an oxide layer, may be preferably a conductive metal oxide such     as ITO, -   2721—an optional reflector (e.g., a Distributed Bragg Reflector), -   2720—a P-type confinement layer that is used for a Green LED (One     example of a material for this region is GaN), -   2718—a buffer layer that is typically used for a Green LED (One     example of a material for this region is AlGaN), -   2716—a multiple quantum well used for a Green LED (One example of     materials for this region are InGaN/GaN), -   2715—a N-type confinement layer that is used for a Green LED (One     example of a material for this region is GaN), -   2752—an oxide layer, may be preferably a conductive metal oxide such     as ITO, -   2710—an oxide layer, may be preferably a conductive metal oxide such     as ITO, -   2709—an optional reflector (e.g., a Distributed Bragg Reflector), -   2708—a P-type confinement layer used for a Red LED (One example of a     material for this region is AlInGaP), -   2706—a multiple quantum well used for a Red LED (One example of     materials for this region are AlInGaP/GaInP), -   2704—a P-type confinement layer used for a Red LED (One example of a     material for this region is AlInGaP), -   2756—an oxide layer, may be preferably a transparent conductive     metal oxide such as ITO, -   2758—a reflector (e.g., aluminum or silver).     Step (B) is illustrated in FIG. 6B. Via holes 2762 are etched to the     substrate layer 2746 to isolate different pixels in the     microdisplay/display. Also, via holes 2760 are etched to make     contacts to various layers of the stack. These via holes may be     preferably filled with a compatible oxide and the surface can be     planarized with CMP. Various elements of FIG. 6B such as 2746, 2744,     2734, 2733, 2732, 2730, 2728, 2727, 2748, 2722, 2721, 2720, 2718,     2716, 2715, 2752, 2710, 2709, 2708, 2706, 2704, 2756 and 2758 have     been described previously.     Step (C) is illustrated in FIG. 6C. Metal 2764 (for example) is     constructed within the via holes 2760 using procedures similar to     those described in respect to FIGS. 4A-4S of parent U.S. patent     application Ser. No. 13/274,161 issued as U.S. Pat. No. 9,197,804,     incorporated herein by reference. Following this construction, an     oxide layer 2766 is deposited. Various elements of FIG. 6C such as     2746, 2744, 2734, 2733, 2732, 2730, 2728, 2727, 2748, 2722, 2721,     2720, 2718, 2716, 2715, 2752, 2710, 2709, 2708, 2706, 2704, 2756,     2760, 2762 and 2758 have been described previously.     Step (D) is illustrated in FIG. 6D. Using procedures described in     co-pending U.S. patent application Ser. No. 12/901,890, issued as     U.S. Pat. No. 8,026,521, the entire contents of which is     incorporated herein by reference, a single crystal silicon     transistor layer 2768 can be monolithically integrated using ion-cut     technology atop the structure shown in FIG. 6C. This transistor     layer 2768 is connected to various contacts of the stacked LED     layers (not shown in the figure for simplicity). Following this     connection, nickel layer 2770 is constructed and solder layer 2772     is constructed. The packaging process then is conducted where the     structure shown in FIG. 6D is connected to a silicon sub-mount. It     can be seen that the structure shown in FIG. 6D can have each pixel     emit a certain color of light by tuning the voltage given to the     red, green and blue layers within each pixel. This microdisplay is     constructed using the ion-cut technology, a smart layer transfer     technique.

The embodiments of this invention described in FIGS. 5-6 may enable novel implementations of “smart-lighting concepts” (also known as visible light communications) that are described in “Switching LEDs on and off to enlighten wireless communications”, EETimes, June 2010 by R. Colin Johnson. For these prior art smart lighting concepts, LED lights could be turned on and off faster than the eye can react, so signaling or communication of information with these LED lights is possible. An embodiment of this invention involves designing the displays/microdisplays described in FIGS. 5-6 to transmit information, by modulating wavelength of each pixel and frequency of switching each pixel on or off. One could thus transmit a high bandwidth through the visible light communication link compared to a LED, since each pixel could emit its own information stream, compared to just one information stream for a standard LED. The stacked RGB LED embodiment described in FIGS. 4A-4S of parent U.S. patent application Ser. No. 13/274,161 issued as U.S. Pat. No. 9,197,804, incorporated herein by reference, could also provide an improved smart-light than prior art since it allows wavelength tunability besides the ability to turn the LED on and off faster than the eye can react.

Optical Interconnects:

Optical interconnects in inter-chip communication have become a feasible replacement for electrical interconnects as the line capacitance of the latter has imposed increasingly difficult limitations due to scaling. As electrical component density increases, optical lines can carry more information between electrical components.

An optical interconnect system may consist of several components. The first is a transmission component that generates and modulates the light that is used to send the information. The second is a network of waveguides that guides the light to the receiving destination on the chip. Finally, there is the receiver network, which converts the light back to electrical signals so that the information can be processed by the electronic devices on the chip.

The transmission component is typically built out of lasers and modulators. Lasers are built typically using III-V semiconductors like GaAs, InP, and InGaAs which have superior optical mechanisms compared to Group IV semiconductors such as silicon or germanium. The drawback with these III-V materials is that their processing is not compatible with the Group IV materials used for the electronic components of the chip. In this case, it may be advantageous that the laser is placed off-chip, which additionally offers the advantage of insulating the laser operation from the temperature variations and power limits of the chip itself. Another option is to use a layer of LEDs in a monolithic 3D configuration as the light sources for the data transmission. The advantage of this option is that LEDs are cheaper than lasers and are easier to modulate directly. However, LEDs present some limitations as to the data transmission efficiency through the waveguides since, unlike the generated light from lasers, the generated light from LEDs are not coherent or collimated, and, hence, waveguide loss is significant.

Waveguides are passive optical components designed to confine light in one direction. Typically they are made out of Silicon, Silicon Dioxide, and Silicon Nitride, which are materials already being used for the electronic components in conventional chips, and thus are materially compatible and can be grown or deposited on top of these layers. So in Silicon-based chips, such dielectric waveguides are usually used, in which a material with high permittivity corresponding to a high index of refraction, is surrounded by a material with lower permittivity corresponding to a lower index of refraction. The structure then guides optical waves by total internal reflection. For example, Silicon may be used for the high permittivity material and Silicon dioxide for the low permittivity material. Another type of waveguides use photonic crystal structures, which again can be constructed using Silicon and Silicon dioxide. In most cases, masks and etching are used to construct the structures. One of the potential disadvantages of dielectric waveguides is they are not able to contain light where sharp turns are required because of the limits imposed on light refraction between two materials by the critical angle, and light leakage may result. So they may be suitable for chip-to-chip optical communications where most waveguides only need to be mostly straight and here the significant distance between the two chips may allow for gradual turns if needed.

Yet another type of waveguides is called hollow metal waveguides (HMWG), made of trenches in the material with walls coated with reflective metals which may include, for example, silver. In combination with beam-splitters, HMWG's allow light to be reflected around sharp corners, which may be a potential advantage as described in Mathai, S., et al., US Patent Application 2009/0244716A1. In intra-chip optical communications, where waveguide layer thickness may be limited, HMWG's may be used to enable the sharp turns required for the light signals.

The receiving component may include an array of photodetectors, typically made from Ge or SiGe. These photodetectors may have a p-n or p-i-n structure and may be biased to capture photons and subsequently convert them into electronic carriers.

Layer transfer technology may be utilized for constructing the layers for an optical interconnect system.

LED-driven chip-to-chip optical interconnect:

The transmission component may consist of a layer of light-emitting diodes (LEDs) physically coupled with a layer of control circuits to manage the triggering of the LEDs so as to control the light being transmitted to enable data communication. The light may then be sent through a layer of waveguides which may distribute the light to their respective destinations on the chip, which may then be received by a layer of photo-detectors and converted to electrical signals by the readout circuits that can be handled by the electronic components of the chip.

FIGS. 7A-7H illustrate an embodiment of the invention, where the transmitter block: LED control circuit layer 3142, LED layer 3148; communication channel: waveguide layer 3136; and receiver block: photo-detector layer 3110, and readout circuit layer 3100 may be stacked monolithically with layer transfer.

The process of forming the optical communication system may include several steps that occur in a sequence from Step A to Step H. Many of these steps share common characteristics, features, modes of operation, etc. When identical reference numbers are used in different drawing figures, they are used to indicate analogous, similar or identical structures to enhance the understanding of the present invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.

Step (A): FIG. 7A illustrates the first step for constructing the photo-detector layer 3110 and readout circuit layer 3100, where the photo-detector layer 3110 may be formed atop the readout circuit layer 3100 using layer transfer. FIG. 7A illustrates a cross-sectional view of silicon wafer substrate with pre-processed read-out circuits 3102, above which an oxide layer 3104 may be deposited. Thus readout circuit layer 3100 is formed. FIG. 7A further illustrates the cross-sectional view of another Silicon wafer 3112 which may have a p+ Silicon layer 3114, a p Silicon layer 3116, a n Silicon layer 3118, a n+ Silicon layer 3120, and an oxide layer 3122. These layers may be formed using procedures similar to those described in FIG. 15A-15G of incorporated parent U.S. Pat. No. 9,197,804. An anneal may then be performed to activate dopants in various layers. Hydrogen may be implanted in the wafer at a certain depth depicted by dashed line 3190.

Step (B): FIG. 7B illustrates the photo-detector and readout circuit structure 3192 formed by an ion-cut layer transfer process. The photo-detector layer 3110 of p+pnn+ silicon consisting of the photo-detector diodes may be layer transferred atop the silicon wafer with readout circuit layer 3100 wherein oxide layer 3104 may be bonded to oxide layer 3122, and p+ silicon layer 3115 may be a result of the cleave and polish operations. Procedures for layer transfer and alignment for forming the structure in FIG. 31B are similar to procedures used for constructing the image sensor shown in FIGS. 15A-15G of incorporated parent U.S. Pat. No. 9,197,804.

Step (C) is illustrated in FIG. 7C. An oxide layer 3124 may be deposited on top of p+ silicon layer 3115. Connections may be made to the terminals of the photo-detector by lithographic, etch, and fill operations similar to those described in FIGS. 15A-15G of incorporated parent U.S. Pat. No. 9,197,804, and are indicated as p+ contact 3126 and n+ contact 3128. Various elements of FIG. 7C such as 3102, 3104, 3115, 3116, 3118, 3120, and 3122 have been described previously herein or in incorporated parent U.S. Pat. No. 9,197,804. Contacts 3130 and interconnects (not shown) for connecting terminals of the photo-detector, such as p+ contact 3124 and p+ contact 3128, to read-out circuits in silicon wafer substrate with pre-processed read-out circuits 3102 may be done. Thus silicon wafer containing the photo-detectors and read-out circuits 3131 may be formed. The functionality of the photo-detectors may be tested at this point.

As described previously, FIGS. 15A-15G of incorporated parent U.S. Pat. No. 9,197,804 illustrate a process whereby oxide vias constructed before layer transfer may be used to look through photo-detector layers to observe alignment marks on the read-out circuit wafer below it. However, an alternative embodiment of this invention may involve constructing oxide vias after layer transfer. Essentially, after layer transfer of structures without oxide vias, oxide vias whose diameters are larger than the maximum misalignment of the bonding/alignment scheme may be formed. This order of sequences may enable observation of alignment marks on the bottom read-out circuit wafer by looking through the photo-detector wafer.

Waveguides are structures designed to confine light in one direction. In Silicon-based chips, dielectric waveguides are usually used, in which a material with high permittivity corresponding to a high index of refraction, is surrounded by a material with lower permittivity corresponding to a lower index of refraction. The structure then guides optical waves by total internal reflection. For Silicon-based chips, convenient materials are Silicon for the high permittivity material and Silicon dioxide for the low permittivity material. Another type of waveguides use photonic crystal structures, which again can be constructed using Silicon and Silicon dioxide. In most cases, masks and etching are used to construct the structures. Yet another type of waveguides may be called hollow metal waveguides (HMWG), made of trenches in the material with walls coated with reflective metals which may include silver. In combination with beam-splitters, HMWG's allow light to be reflected around sharp corners, which may be a potential advantage.

Step (D) is illustrated in FIG. 7D. Silicon waveguides 3136 may be formed on the SOI wafer 3132 and BOX 3134 by electron beam lithography followed by electron cyclotron resonance plasma etching. The wafer may then be coated with Silicon Dioxide 3138 to form the over-cladding. It will be obvious to one skilled in the art that many configurations and material combinations are being currently used and/or possible in the formation of the waveguides. This invention is not limited to one particular configuration or set of materials. Hydrogen may be implanted in the wafer at a certain depth depicted by 3140. Thus, Silicon/Silicon Dioxide waveguide layer 3139 may be formed.

Step (E) is illustrated in FIG. 7E. The Silicon/Silicon Dioxide waveguide layer 3139 may then be ion-cut layer transferred atop the silicon wafer containing the photo-detectors and read-out circuits 3131. Procedures for layer transfer and alignment for forming the structure 3141 in FIG. 7E are similar to procedures used previously herein and/or in incorporated parent U.S. Pat. No. 9,197,804: Silicon/Silicon Dioxide waveguide layer 3139 may be flipped and bonded atop silicon wafer containing the photo-detectors and read-out circuits 3131 using oxide-oxide bonding and the Silicon substrate 3132 may then be cleaved and polished until the oxide layer 3134, now labeled 3135 after the cleave and polish process, is reached.

Step (F) is shown in FIG. 7F which is used for constructing the LED and control circuit layers, where the Red LED layer from Red LED wafer 3148 may be formed atop the electronic control circuit layer 3142 using ion-cut layer transfer. Silicon wafer with control circuits 3144 may be conventionally constructed, above which an oxide layer 3146 may be deposited. Red LED wafer 3148 may include GaAs wafer 3150, n-type confinement layer 3152, multiple quantum well (MQW) layer 3154, P-type confinement layer 3156, and an ITO current spreader layer 3158. Examples of materials used to construct these layers may include, but are not limited to; doped AlInGaP for the n-type confinement layer 3152 and p-type confinement layer 3156, multiple quantum well layer 3154 could be composed of AlInGaP and GaInP. These layers may be formed by processes such as molecular beam epitaxy, MOCVD, etc. The red LED wafer described in FIG. 7F may have hydrogen implanted into it at a certain depth as shown by dotted line 3160. Alternatively, helium can be implanted.

Step (G) is shown in FIG. 7G. The layer of GaAs structures consisting of the red LEDs 3148 may be layer transferred atop the silicon wafer with the control circuits 3142 forming the LED stack 3170. Procedures for layer transfer and alignment for forming the structure in FIG. 7G may be similar to procedures used for constructing the LED lighting shown in FIGS. 12A-12F of incorporated parent U.S. Pat. No. 9,197,804. n-GaAs layer 3152 is renamed 3153 after the cleaving and polishing process. An ITO layer 3162 is deposited atop n-GaAs layer 3153, thus forming the LED stack 3170. The functionality of the LEDs may be tested at this point.

Step (H) is illustrated by FIG. 7H. The structure shown in FIG. 31G, LED stack 3170, may be flipped and bonded atop the structure shown in FIG. 7E, structure 3141, using oxide-to-oxide bonding of ITO layer 3162 and oxide layer 3135. Various elements in FIG. 7H such as 3102, 3104, 3115, 3116, 3118, 3120, 3122, 3124, 3135, 3136, 3138, 3144, 3146, 3153, 3154, 3156, 3158 and 3162 have been described previously herein and/or in incorporated parent U.S. Pat. No. 9,197,804. Thus, LED-driven chip-to-chip optical interconnect 3199 may be formed.

Laser-driven chip-to-chip optical interconnect:

FIGS. 8A-8D illustrate an embodiment of this invention, where the transmitter block: modulator control circuit layer 3242, modulator layer 3248; communication channel: waveguide layer 3236; and receiver block: photodetector layer 3210, and readout circuit layer 3200 are stacked monolithically with layer transfer.

Step (A): FIG. 8A illustrates the first step for constructing the waveguide layer 3236, photodetector layer 3210, readout circuit layer 3200, where the waveguide layer 3236 with oxide layer 3234, oxide layer 3228, oxide layer 3221 oxide layer 3222 and oxide layer 3204 may be formed atop the photodetector layer 3210, which in turn may be formed atop the readout circuit layer 3200 using layer transfer procedures described in FIG. 7A-7E.

Step (B) is shown in FIG. 8B which is used for constructing the modulator and control circuit layers, where the modulator layer is formed atop the electronic control circuit layer using layer transfer. 3242 shows a cross-sectional view of 3244, a silicon wafer with control circuits constructed on it, above which an oxide layer 3246 is deposited. 3248 shows the cross-sectional view of a Silicon wafer 3250 containing Silicon-Germanium modulators and may include a P-type Silicon-Germanium buffer layer 3252, an undoped Silicon-Germanium spacer 3254, a Germanium/Silicon-Germanium multiple quantum well (MQW) 3256, another undoped Silicon-Germanium spacer 3258, an N-type Silicon-Germanium layer 3260, and a deposited oxide layer 3262. Examples of materials used to construct these layers, include, but are not limited to, doped GaAs for the N-type cap layer 3260 and P-type buffer layer 3252, the multiple quantum well layer 3256 could be of GaAs and AlGaAs. A double heterostructure configuration or single quantum well configuration could be used instead of a multiple quantum well configuration. Various other material types and configurations could be used for constructing the modulators for this process. The modulator wafer described in FIG. 8B has hydrogen implanted into it at a certain depth. The dotted line 3264 depicts the hydrogen implant. Alternatively, helium can be implanted.

Step (C) is shown in FIG. 8C. The layer of SiGe structures consisting of the modulators 3248 is layer transferred atop the silicon wafer with the control circuits 3242. Procedures for layer transfer and alignment for forming the structure in FIG. 8C are similar to procedures used for constructing the photo-detectors shown in FIGS. 15A-G of incorporated parent U.S. Pat. No. 9,197,804. The functionality of the modulators can be tested at this point.

Step (D) is illustrated by FIG. 8D. The structure shown in FIG. 8C is flipped and bonded atop the structure shown in FIG. 8A using oxide-to-oxide bonding of layers 3266 and 3234. Various elements in FIG. 32D such as 3202, 3204, 3214, 3216, 3218, 3220, 3222, 3234, 3236, 3238, 3244, 3246, 3252, 3254, 3256, 3258, 3260, 3262 and 3266 have been described previously herein and/or within incorporated parent U.S. Pat. No. 9,197,804. An external laser 3268 (typically made of InP) is then coupled to the structure via an optical fiber 3270 by known techniques.

On-chip LED-driven Optical Interconnects

FIGS. 9A-9C illustrate an embodiment of this invention, where the LED-driven optical communication is among sections on a single chip.

FIG. 9A illustrates a cross-sectional view of a transmitter section 3350 and a receiver section 3360. The transmitter section 3350 may include LED control circuit layer 3352, LED layer 3354 and waveguide layer 3356 stacked monolithically with layer transfer. The receiver section 3360 may contain readout circuit layer 3362, photo-detector layer 3364 and waveguide layer 3166 stacked monolithically with layer transfer. Layer transfer procedures are similar to those described in FIGS. 7A-7H herein.

FIG. 9B illustrates an exemplary top view of integrated circuit chip 3310 which may include integrated circuits 3312, optical transmitters using LEDs 3314 and 3316, optical receivers using photo-detectors 3318 and 3320, and waveguide sections 3322 and 3324 enabling optical communication from one end of the chip to the other.

FIG. 9C illustrates a cross-sectional view (not to scale) of an integrated circuit chip 3330 with a substrate 3332, control and readout circuit sections 3338 and 3340, integrated circuit section 3334, LED and photo-detector layer 3336, and waveguide layer 3342. Persons of ordinary skill in the art will appreciate that each layer may use the same material throughout the layer for ease of processing, but may differ among different layers. As an example, the waveguide layer 3342 may use Silicon, the LED and photo-detector layer 3336 may use III-V semiconductor material, the layer with control and readout circuit sections 3338 and 3340 and integrated circuits section 3334 may use Silicon, and the substrate 3332 may use silicon.

FIG. 10 illustrates cross-sectional view of a waveguide structure 3470 with Hollow-metal waveguide (HMWG) 3472, beam-splitters 3474 and 3476 and light signal 3478. HMWG with reflective metal coating and beam-splitters are capable of guiding light through sharp turns by allowing sharp-angled reflections which may be a potential advantage compared to dielectric waveguides when waveguide layer thickness is in consideration.

On-chip Laser-Driven Optical Interconnects

FIGS. 11A-11C illustrate an embodiment of this invention, where the laser-driven optical communication is among sections on a single chip.

FIG. 11A illustrates a cross-sectional view of a transmitter section 3550 and a receiver section 3560. The transmitter section 3550 may include modulator control circuit layer 3552, modulator layer 3554 and waveguide layer 3556 stacked monolithically with layer transfer, external laser 3558, fiber-optic coupling 3559 (connecting external laser 3559 to modulator layer 3554). The receiver section 3560 may contain a readout circuit layer 3562, photo-detector layer 3564 and waveguide layer 3566 stacked monolithically with layer transfer. Layer transfer procedures are similar to those described in FIG. 8A-8D herein.

FIG. 11B illustrates an exemplary top view of integrated circuit chip 3510 which may include integrated circuits 3512, optical transmitters using external laser 3526, fiber-optic couplings 3528 and 3529, modulators 3514 and 3516, optical receivers using photo-detectors 3518 and 3520, and waveguide sections 3522 and 3524 enabling optical communication from one end of the chip to the other.

FIG. 11C illustrates a cross-sectional view (not to scale) of an integrated circuit chip 3530 with substrate 3532, control and readout circuit sections 3538 and 3540, integrated circuit section 3534, modulator and photo-detector layer 3536, waveguide layer 3542, external laser 3544 and fiber-optic coupling 3546. Persons of ordinary skill in the art will appreciate that each layer may use the same material throughout the layer for ease of processing, but may differ among different layers. As an example, the waveguide layer 3542 may use Silicon, the modulator and photo-detector layer 3536 may use III-V semiconductor material, the layer with control and readout circuit sections 3538 and 3540 and integrated circuits section 3534 may use Silicon, and the substrate 3532 may use silicon.

As described in FIG. 10 , the waveguide layer may use HMWGs with reflective metal coating and beam-splitters capable of guiding light through sharp turns by allowing sharp-angled reflections which may be a potential advantage compared to dielectric waveguides when waveguide layer thickness is in consideration.

Persons of ordinary skill in the art will appreciate that while Silicon has been suggested as the material for the photo-detector layer of FIG. 7A, Germanium or Silicon-Germanium could be utilized. The advantage of Germanium is that it is sensitive to infra-red wavelengths as well. However, Germanium also suffers from high dark current. Moreover, the photo-detector layer 3110 is denoted as a p-n junction layer; however, any type of photo-detector layer, such as a p-i-n layer or some other type of photo-detector can be used. Furthermore, the thickness of the photo-detector layer may be typically less than approximately 5 μm, but may also be greater. Moreover, a double hetero-structure configuration or single quantum well configuration could be used instead of a multiple quantum well configuration such as the shown multiple quantum well layer 3154. Further, various other material types and configurations, such as GaAs, AlInGaP, and GaInP, could be used for constructing the red LEDs for this process. Thus the invention is to be limited only by the appended claims.

Several material systems have been illustrated as examples for various embodiments of this invention in this patent application. It will be clear to one skilled in the art based on the present disclosure that various other material systems and configurations can also be used without violating the concepts described. It will also be appreciated by persons of ordinary skill in the art that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the invention includes both combinations and sub-combinations of the various features described herein above as well as modifications and variations which would occur to such skilled persons upon reading the foregoing description. Thus the invention is to be limited only by the appended claims. 

We claim:
 1. A multi-level semiconductor device, the device comprising: a first level comprising integrated circuits; a second level comprising a structure designed to conduct electromagnetic waves, wherein said second level is disposed above said first level, wherein said integrated circuits comprise single crystal transistors; and an oxide layer disposed between said first level and said second level, wherein said second level is bonded to said oxide layer, and wherein said bonded comprises oxide to oxide bonds.
 2. The device according to claim 1, wherein said structure is designed to conduct said electromagnetic waves in a confined manner.
 3. The device according to claim 1, wherein said structure comprises an electromagnetic waveguide.
 4. The device according to claim 1, further comprising: a third level comprising a crystalline silicon layer, wherein a thickness of said crystalline silicon layer is less than 60 microns.
 5. The device according to claim 1, wherein said device comprises a crystalline III-V material.
 6. The device according to claim 1, further comprising: a transmitter disposed within said second level, wherein said transmitter comprises at least one modulator.
 7. The device according to claim 1, further comprising: a third level, wherein said third level comprises a layer comprising electronic circuits.
 8. A multi-level semiconductor device, the device comprising: a first level comprising a structure designed to conduct electromagnetic waves; a second level comprising integrated circuits, wherein said second level is disposed above said first level, wherein said integrated circuits comprise single crystal transistors; and an oxide layer disposed between said first level and said second level, wherein said second level is bonded to said oxide layer, and wherein said bonded comprises oxide to oxide bonds.
 9. The device according to claim 8, wherein said structure is designed to conduct said electromagnetic waves in a confined manner.
 10. The device according to claim 8, wherein said structure comprises an electromagnetic waveguide.
 11. The device according to claim 8, further comprising: a third level comprising a crystalline silicon layer, wherein a thickness of said crystalline silicon layer is less than 60 microns.
 12. The device according to claim 8, wherein said device comprises a crystalline III-V material.
 13. The device according to claim 8, further comprising: a transmitter disposed within said second level, wherein said transmitter comprises at least one modulator.
 14. The device according to claim 8, further comprising: a third level, wherein said third level comprises a layer comprising electronic circuits.
 15. A multi-level semiconductor device, the device comprising: a first level comprising integrated circuits and communication control circuits; a second level comprising a plurality of interconnect lines, wherein said second level is disposed above said first level, wherein said first level comprises a crystalline material; an oxide layer disposed between said first level and said second level, wherein said second level is bonded to said first level, wherein said bonded comprises oxide to oxide bonds; and at least one electromagnetic wave receiver.
 16. The device according to claim 15, wherein said plurality of interconnect lines are designed to conduct electromagnetic waves in a confined manner.
 17. The device according to claim 15, further comprising: a third level comprising a crystalline silicon layer, wherein a thickness of said crystalline silicon layer is less than 60 microns.
 18. The device according to claim 15, wherein said device comprises a crystalline III-V material.
 19. The device according to claim 15, further comprising: a transmitter circuit disposed within said second level, wherein said transmitter circuit comprises at least one modulator.
 20. The device according to claim 15, further comprising: a third level, wherein said third level comprises a layer comprising electronic circuits. 